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Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12DP256BDGV2/D
MC9S12DP256B Device User Guide V02.15 Covers also
Freescale Semiconductor, Inc...
MC9S12DT256C, MC9S12DJ256C, MC9S12DG256C, MC9S12DT256B, MC9S12DJ256B, MC9S12DG256B MC9S12A256B
Original Release Date: 29 Mar 2001 Revised: Jan 11, 2005 Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
DOCUMENT NUMBER 9S12DP256BDGV2/D
Revision History
Version Revision Effective Number Date Date
V01.00 29 MAR 2001 8 MAY 2001 29 MAR 2001 8 MAY 2001
Author
Initial version.
Description of Changes
V01.01
Freescale Semiconductor, Inc...
VDD5 spec change 4.5V . . 5.25V Current Injection on single pin +- 2.5mA added DC bias level on EXTAL pin minor cosmetics and corrected typos changed ATD Electrical Characteristics seperate coupling ratio for positive and negative bulk current injection added pinout for 80QFP corrected SPI timing corrected Expanded Bus Timing Characteristics Some corrections on pin usage after review Minor corrections with respect to format and wording Added SRAM data retention disclaimer Changed Oscillator Characteristics tCQOUT max 2.5s and replaced Clock Monitor Time-out by Clock Monitor Failure Assert Frequency Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz Changed IDDPS (RTI and COP disabled) to 400uA Corrected fref and REFDV/SYNR Settings for PLL Stabilization Delay Measurements, added tEXTR and tEXTF to Oscillator Characteristics, Corrected tEXTL and tEXTH values Added thermal resistance for LQFP 80, added PCB layout proposal for power and ground connections Added Document Names Variable definitions and Names have been hidden Added Maskset 1K79X Modified description in chapter A.5.2 Oscillator
V02.00
16 May 2001 5 June 2001 14 June 2001 18 June 2001 26 June 2001
16 May 2001
V02.01 V02.02 V02.03
V02.04
V02.05
11 July 2001 17 July 2001 24 July 2001
V02.06
V02.07
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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Freescale Semiconductor, Inc.9S12DP256BDGV2/D V02.15 MC9S12DP256B Device User Guide --
Version Revision Effective Number Date Date
V02.08 24 August 2001
Author
Description of Changes
Corrected local enable bits in interrupt vector table Corrected #33 - #36 in table A-20 A.4 Voltage Regulator characteristics was removed A.1 to A.7 major rework according to feedback from PE Changed document name and title to MC9.. Added table containing other devices covered by this document Added NVM Blank check specificaiton Added external ADC trigger to pin description Updated A-7 Supply Current Characteristics Updated Table0-1 Derivative Differences Added Item8 to Table A-8 IOL/IOH reduced to 10mA/2mA for full/reduced drive Changed ATD characteristic Cins max to 22pF Changed VDD min VDDPLL min to 2.35V Removed Oscillator startup time from POR or STOP changed input capacitance for standard i/o pin to 6pF Corrected NVM reliability spec added derivative differences for part number MC9S12D256C added partID and maskset number for MC9S12D256D added table with fixed defects on 2K79X added table for HCS12 core configuration Added detailed register map Added pull device description to signal table corrected tables 0-1 and 0-2 Derivative Differences added 80QFP DG256 pin assignment diagram added A256B parts to table 0-1 Derivative Differences removed protected sector definition from table 1-1
V02.09
12 Nov 2001
Freescale Semiconductor, Inc...
V02.10
28 Feb 2002 26 Mar 2002
V02.11
V02.12
12 Aug 2002
V02.13 V02.14 V02.15
25 Sep 2002 28 Feb 2003 11 Jan 2005
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Freescale Semiconductor, MC9S12DP256B Device User Guide -- 9S12DP256BDGV2/D V02.15
Inc.
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Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.4 VREGEN -- Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.5 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . .60 2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .60 2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .61 2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .61 2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .61 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .61 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.16 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.18 PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.19 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.20 PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56
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PH7 / KWH7 / SS2 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PH3 / KWH3 / SS1 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .63 PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .64 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PK7 / ECS / ROMONE -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PM7 / TXCAN3 / TXCAN4 -- Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PM6 / RXCAN3 / RXCAN4 -- Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5. . . . . . . . . . . . . . .64 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4. . . . . . . . . . . . . .64 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .65 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .65 PM1 / TXCAN0 / TXB -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PM0 / RXCAN0 / RXB -- Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .65 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .66 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .66 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .66 PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
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2.3.57 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .68 2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 68 2.4.3 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .68 2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.4.7 VREGEN -- On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
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Section 3 System Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Section 4 Modes of Operation
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Section 6 HCS12 Core Block Description
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Section 7 Clock and Reset Generator (CRG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Section 8 Enhanced Capture Timer (ECT) Block Description Section 9 Analog to Digital Converter (ATD) Block Description Section 10 Inter-IC Bus (IIC) Block Description Section 11 Serial Communications Interface (SCI) Block Description
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Section 12 Serial Peripheral Interface (SPI) Block Description Section 13 J1850 (BDLC) Block Description Section 14 Pulse Width Modulator (PWM) Block Description Section 15 Flash EEPROM 256K Block Description Section 16 EEPROM 4K Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Section 20 Voltage Regulator (VREG) Block Description Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
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A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Appendix B Package Information
B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
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List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 3-1 Figure 20-1 Figure 20-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 MC9S12DP256B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 MC9S12DP256B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Pin Assignments in 80-pin QFP for MC9S12DG256 . . . . . . . . . . . . . . . . . . . . . .55 Pin Assignments in 80-pin QFP for MC9S12DJ256 . . . . . . . . . . . . . . . . . . . . . .56 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Recommended PCB Layout 112 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Recommended PCB Layout for 80QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 124 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 125
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List of Tables
Table 0-1 Table 0-2 Table 0-4 Table 0-3 Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 2-1 Table 2-2 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 6-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Drivative Differences MC9S12D256B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Derivative Differences MC9S12D256C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Defects fixed on Maskset 2K79X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .41 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 MC9S12DP256 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . .69 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Configuration of HCS12 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . .105 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
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Preface
The Device User Guide provides information about the MC9S12DP256B device made up of standard HCS12 blocks and the HCS12 processor core. Table 0-1 and Table 0-2 show the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Drivative Differences MC9S12D256B
Generic device
# of CANs
MC9S12DP256B
5
MC9S12DT256B
3
MC9S12DJ256B
2
MC9S12DG256B
2
MC9S12A256B
0
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CAN0 CAN1 CAN2 CAN3 CAN4 J1850/BDLC Package Mask set Temp Options package Code Notes

112 LQFP 0/1K79X M, V, C PV

112 LQFP 0/1K79X M, V, C PV

112 LQFP/80 QFP 0/1K79X M, V, C PV/FU
112 LQFP/80 QFP 0/1K79X M, V, C PV 112 LQFP/80 QFP 0/1K79X C PV/FU
An errata exists An errata exists An errata exists An errata exists An errata exists conntact Sales office conntact Sales office conntact Sales office conntact Sales office conntact Sales office
Table 0-2 Derivative Differences MC9S12D256C
Generic device
# of CANs CAN0 CAN1 CAN2 CAN3 CAN4 J1850/BDLC Package Mask set Temp Options package Code Notes
MC9S12DP256C
5
MC9S12DT256C
3
MC9S12DJ256C
2
MC9S12DG256C
2

112 LQFP 2K79X M, V, C PV

112 LQFP 2K79X M, V, C PV

112 LQFP/80 QFP 2K79X M, V, C PV/FU
112 LQFP/80 QFP 2K79X M, V, C PV
An errata exists An errata exists An errata exists An errata exists conntact Sales office conntact Sales office conntact Sales office conntact Sales office
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Table 0-3 shows the defects fixed on maskset 2K79X (MC9S12DP256C) Table 0-3 Defects fixed on Maskset 2K79X
Defect MUCts00510 MUCts00604 MUCts00603 Headline SCI interrupt asserts only if odd number of interrupts active Security in Normal Single Chip mode Security in Normal Single Chip mode
This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document.
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MC9S12 DP256C C FU
Package Option Temperature Option Device Title Controller Family
Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Package Options FU = 80QFP PV = 112 LQFP
Figure 0-1 Order Part Number Example See Table 0-4 for names and versions of the referenced documents throughout the Device User Guide. Table 0-4 Document References
User Guide
HCS12 V1.5 Core User Guide CRG Block User Guide ECT_16B8C Block User Guide ATD_10B8C Block User Guide IIC Block User Guide SCI Block User Guide SPI Block User Guide PWM_8B8C Block User Guide FTS256K Block User Guide EETS4K Block User Guide BDLC Block User Guide MSCAN Block User Guide VREG Block User Guide PIM_9DP256 Block User Guide
Version
1.2 V02 V01 V02 V02 V02 V02 V01 V02 V02 V01 V02 V01 V02
Document Order Number
HCS12COREUG S12CRGV2/D S12ECT16B8CV1/D S12ATD10B8CV2/D S12IICV2/D S12SCIV2/D S12SPIV2/D S12PWM8B8CV1/D S12FTS256KV2/D S12EETS4KV2/D S12BDLCV1/D S12MSCANV2/D S12VREGV1/D S12PIM9DP256V2/D
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Section 1 Introduction
1.1 Overview
The MC9S12DP256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability, five CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. The MC9S12DP256 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
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1.2 Features
* HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing - - - - - * * MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints) BDM (Background Debug Mode)
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) 8-bit and 4-bit ports with interrupt functionality - - Digital filtering Programmable rising or falling edge trigger 256K Flash EEPROM 4K byte EEPROM 12K byte RAM
*
Memory - - -
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*
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Two 8-channel Analog-to-Digital Converters - - 10-bit resolution External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Two asynchronous Serial Communications Interfaces (SCI) Three Synchronous Serial Peripheral Interface (SPI) SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications Compatible with I2C Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies I/O lines with 5V input and drive capability
*
Five 1M bit per second, CAN 2.0 A, B software compatible modules - - - - -
*
Enhanced Capture Timer - - -
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*
8 PWM channels - - - - - - -
*
Serial interfaces - -
*
Byte Data Link Controller (BDLC) -
*
Inter-IC Bus (IIC) - - -
*
112-Pin LQFP package -
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- - - - - 5V A/D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single-wire background debugTM mode (BDM) On-chip hardware breakpoints
V02.15
1.3 Modes of Operation
User modes * Normal and Emulation Operating Modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only)
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Special Operating Modes
Low power modes * * * Stop Mode Pseudo Stop Mode Wait Mode
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1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DP256B device.
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Figure 1-1 MC9S12DP256B Block Diagram
256K Byte Flash EEPROM 12K Byte RAM 4K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
V02.15
ATD0
VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
Voltage Regulator
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
AD0
Single-wire Background Debug Module
Clock and Reset Generation Module
CPU12
DDRK
PPAGE
PLL
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Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PTK
AD1
ECS
XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
PTE
Enhanced Capture Timer
DDRT DDRS
SCI0
PTS
SCI1 Multiplexed Address/Data Bus SPI0 DDRA PTA
DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0 MISO MOSI SCK SS RXB TXB RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN
PTT
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
CAN0 CAN1 CAN2 CAN3
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Module to Port Routing
BDLC (J1850)
Multiplexed Wide Bus
CAN4
IIC
SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS
Internal Logic 2.5V
VDD1,2 VSS1,2
I/O Driver 5V
VDDX VSSX
PTJ
Multiplexed Narrow Bus
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DDRP
DDRJ
PLL 2.5V
VDDPLL VSSPLL
A/D Converter 5V & Voltage Regulator Reference
VDDA VSSA
PWM
Voltage Regulator 5V & I/O
VDDR VSSR
SPI1
PTP
DDRH
PH2
PTH
PH3 PH4 PH5 PH6 PH7
SPI2
Signals shown in Bold are not available on the 80 Pin Package
DDRM
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
PTM
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Semiconductor, Inc.
1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP256B after reset. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space. Table 1-1 Device Memory Map
Address
$0000 - $0017 $0018 - $0019 Reserved
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size (Bytes)
24 2 2 4 8 8 4 12 64 32 40 8 8 8 8 8 8 8 16 12 4 32 64 64 64 64 64 64 320 4096 12288 16384 16384 16384
$001A - $001B Device ID register (PARTID)
Freescale Semiconductor, Inc...
$001C - $001F CORE (MEMSIZ, IRQ, HPRIO) $0020 - $0027 $0028 - $002F $0030 - $0033 $0034 - $003F $0040 - $007F $0080 - $009F Reserved CORE (Background Debug Mode) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0)
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) $00C8 - $00CF Serial Communications Interface 0 (SCI0) $00D0 - $00D7 Serial Communications Interface 0 (SCI1) $00D8 - $00DF Serial Peripheral Interface (SPI0) $00E0 - $00E7 Inter IC Bus $00E8 - $00EF Byte Data Link Controller (BDLC) $00F0 - $00F7 $00F8 - $00FF $0100- $010F $0110 - $011B $0120 - $013F $0140 - $017F $0180 - $01BF $0200 - $023F $0240 - $027F $0280 - $02BF $0000 - $0FFF $1000 - $3FFF $4000 - $7FFF Serial Peripheral Interface (SPI1) Serial Peripheral Interface (SPI2) Flash Control Register EEPROM Control Register Analog to Digital Converter 10-bit 8 channels (ATD1) Motorola Scalable Can (CAN0) Motorola Scalable Can (CAN1) Motorola Scalable Can (CAN3) Port Integration Module (PIM) Motorola Scalable Can (CAN4) EEPROM array RAM array Fixed Flash EEPROM
$011C - $011F Reserved
$01C0 - $01FF Motorola Scalable Can (CAN2)
$02C0 - $03FF Reserved
$8000 - $BFFF Flash EEPROM Page Window $C000 - $FFFF Fixed Flash EEPROM
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
V02.15
Figure 1-2 MC9S12DP256B Memory Map
$0000 $0400
$03FF $0000 $0000
REGISTERS
(Mappable to any 2k Block within the first 32K)
$1000
$0FFF $1000
4K Bytes EEPROM
(Mappable to any 4K Block)
12K Bytes RAM
(Mappable to any 16K and alignable to top or bottom)
$4000
Freescale Semiconductor, Inc...
$3FFF $4000
16K Fixed Flash Page $3E = 62
(This is dependant on the state of the ROMHM bit)
$7FFF
$8000
$8000
EXTERN
$BFFF
16K Page Window 16 x 16K Flash EEPROM pages
$C000
$C000
16K Fixed Flash Page $3F = 63
$FFFF $FF00
$FF00 VECTORS $FFFF EXPANDED* NORMAL SINGLE CHIP SPECIAL SINGLE CHIP VECTORS VECTORS
$FFFF
BDM (if active)
* Assuming that a `0' was driven onto port K bit 7 during MCU
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Freescale MC9S12DP256B Device User Guide -- V02.15
Semiconductor, Inc.
1.6 Detailed Register Map
The following tables show the detailed register map of the MC9S12DP256B. $0000 - $000F
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI map 1 of 3 (Core User Guide)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0
Freescale Semiconductor, Inc...
$0010 - $0014
Address Name
MMC map 1 of 4 (Core User Guide)
Bit 5 RAM13 REG13 Bit 4 RAM12 REG12 Bit 3 RAM11 REG11 Bit 2 0 0 Bit 1 0 0 Bit 0 RAMHAL 0
Bit 7 Bit 6 Read: $0010 RAM15 RAM14 INITRM Write: Read: 0 $0011 is reset INITRG expanded wide or narrow mode. REG14 into normal Write:
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0010 - $0014
Address $0012 $0013 $0014 Name INITEE MISC MTST0 Read: Write: Read: Write: Read: Write:
V02.15
MMC map 1 of 4 (Core User Guide)
Bit 7 EE15 0 Bit 7 Bit 6 EE14 0 6 Bit 5 EE13 0 5 Bit 4 EE12 0 4 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 EEON
EXSTR1 EXSTR0 ROMHM ROMON 3 2 1 Bit 0
$0015 - $0016
Address $0015 Name ITCR ITEST Read: Write: Read: Write:
INT map 1 of 2 (Core User Guide)
Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
Freescale Semiconductor, Inc...
$0016
$0017 - $0017
Address $0017 Name MTST1 Read: Write:
MMC map 2 of 4 (Core User Guide)
Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0
$0018 - $001B
Address $0018 $0019 $001A $001B Name Reserved Reserved PARTIDH PARTIDL Read: Write: Read: Write: Read: Write: Read: Write:
Miscellaneous Peripherals (Device User Guide,Table 1-3)
Bit 7 0 0 ID15 ID7 Bit 6 0 0 ID14 ID6 Bit 5 0 0 ID13 ID5 Bit 4 0 0 ID12 ID4 Bit 3 0 0 ID11 ID3 Bit 2 0 0 ID10 ID2 Bit 1 0 0 ID9 ID1 Bit 0 0 0 ID8 ID0
$001C - $001D
Address $001C $001D Name MEMSIZ0 MEMSIZ1
MMC map 3 of 4 (Core and Device User Guide,Table 1-4)
Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0
$001E - $001E
Address $001E Name INTCR Read: Write:
MEBI map 2 of 3 (Core User Guide)
Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
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Freescale MC9S12DP256B Device User Guide -- V02.15
$001F - $001F
Address $001F Name HPRIO Read: Write:
Semiconductor, Inc.
INT map 2 of 2 (Core User Guide)
Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0
$0020 - $0027
Address $0020 $0021 $0022 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read Write:
Reserved
Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0
Freescale Semiconductor, Inc...
$0023 $0024 $0025 $0026 $0027
$0028 - $002F
Address $0028 $0029 $002A $002B $002C $002D $002E $002F Name BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L
BKP (Core User Guide)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write:
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
V02.15
MMC map 4 of 4 (Core User Guide)
Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
$0032 - $0033
Address $0032 $0033 Name PORTK DDRK Read: Write: Read: Write:
MEBI map 3 of 3 (Core User Guide)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
Freescale Semiconductor, Inc...
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
CRG (Clock and Reset Generator)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 Write: Read: 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 Write: Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 Write: Read: 0 LOCK TRACK SCM RTIF PROF LOCKIF SCMIF Write: Read: 0 0 0 0 0 RTIE LOCKIE SCMIE Write: Read: PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Write: Read: 0 CME PLLON AUTO ACQ PRE PCE SCME Write: Read: 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Write: Read: 0 0 0 WCOP RSBCK CR2 CR1 CR0 Write: Read: 0 0 0 0 RTIBYP COPBYP PLLBYP FCM Write: Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0 Write: Read: 0 0 0 0 0 0 0 0 Write: Bit 7 6 5 4 3 2 1 Bit 0
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Freescale MC9S12DP256B Device User Guide -- V02.15
$0040 - $007F
Address $0040 $0041 $0042 $0043 $0044 $0045 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0 13 5 13 5 13 5 13 5 13 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0 12 4 12 4 12 4 12 4 12 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 0 TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8
Freescale Semiconductor, Inc...
$0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0040 - $007F
Address $0059 $005A $005B $005C $005D $005E Name TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG
V02.15
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Bit 7 Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: MCZI Write: Read: MCZF Write: Read: 0 Write: Read: 0 Write: Read: NOVW7 Write: Read: SH37 Write: Read: Write: Read: 0 Write: Read: Write: Read: Write: Read: 0 Write: Read: 0 Write: Bit 6 6 14 6 14 6 14 6 PAEN 0 6 6 6 6 MODMC 0 0 0 NOVW6 SH26 Bit 5 5 13 5 13 5 13 5 PAMOD 0 5 5 5 5 RDMCL 0 0 0 NOVW5 SH15 Bit 4 4 12 4 12 4 12 4 PEDGE 0 4 4 4 4 0 ICLAT 0 0 0 NOVW4 SH04 Bit 3 3 11 3 11 3 11 3 CLK1 0 3 3 3 3 0 FLMC POLF3 PA3EN 0 NOVW3 TFMOD Bit 2 2 10 2 10 2 10 2 CLK0 0 2 2 2 2 MCEN POLF2 PA2EN 0 NOVW2 PACMX Bit 1 1 9 1 9 1 9 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 PA1EN DLY1 NOVW1 BUFEN Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0 PA0EN DLY0 NOVW0 LATQ
Freescale Semiconductor, Inc...
$005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F $0070 $0071
0
0
0
0
0
TCBYP
0
PBEN 0
0 0
0 0
0 0
0 0
PBOVI PBOVF
0 0
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Freescale MC9S12DP256B Device User Guide -- V02.15
$0040 - $007F
Address $0072 $0073 $0074 $0075 $0076 $0077 Name PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 6 6 6 6 14 6 14 6 14 6 14 6 14 6 Bit 5 5 5 5 5 13 5 13 5 13 5 13 5 13 5 Bit 4 4 4 4 4 12 4 12 4 12 4 12 4 12 4 Bit 3 3 3 3 3 11 3 11 3 11 3 11 3 11 3 Bit 2 2 2 2 2 10 2 10 2 10 2 10 2 10 2 Bit 1 1 1 1 1 9 1 9 1 9 1 9 1 9 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
Freescale Semiconductor, Inc...
$0078 $0079 $007A $007B $007C $007D $007E $007F
$0080 - $009F
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $008B Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 S1C PRS3 0 0 0
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0080 - $009F
Address $0088 $0089 $008A $008B $008C $008D Name ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved PORTAD0 ATD0DR0H ATD0DR0L ATD0DR1H ATD0DR1L ATD0DR2H ATD0DR2L ATD0DR3H ATD0DR3L ATD0DR4H ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H ATD0DR6L ATD0DR7H ATD0DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
V02.15
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 0 0 0 CCF7 0 Bit 7 0 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 0 0 0 CCF6 0 6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 0 0 CCF5 0 5 0 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 0 0 0 CCF4 0 4 0 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 0 0 0 CCF3 0 3 0 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 0 0 0 CCF2 0 2 0 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 0 0 0 CCF1 0 1 0 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 0 SC 0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0
Freescale Semiconductor, Inc...
$008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F
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Freescale MC9S12DP256B Device User Guide -- V02.15
$00A0 - $00C7
Address $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 Name
Semiconductor, Inc.
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
$00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 $00B8
Bit 7 Read: PWME7 PWME Write: Read: PPOL7 PWMPOL Write: Read: PCLK7 PWMCLK Write: Read: 0 PWMPRCLK Write: Read: CAE7 PWMCAE Write: Read: CON67 PWMCTL Write: PWMTST Read: 0 Test Only Write: Read: 0 PWMPRSC Write: Read: Bit 7 PWMSCLA Write: Read: Bit 7 PWMSCLB Write: Read: 0 PWMSCNTA Write: Read: 0 PWMSCNTB Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Read: Bit 7 PWMCNT3 Write: 0 Read: Bit 7 PWMCNT4 Write: 0 Read: Bit 7 PWMCNT5 Write: 0 Read: Bit 7 PWMCNT6 Write: 0 Read: Bit 7 PWMCNT7 Write: 0 Read: Bit 7 PWMPER0 Write: Read: Bit 7 PWMPER1 Write: Read: Bit 7 PWMPER2 Write: Read: Bit 7 PWMPER3 Write: Read: Bit 7 PWMPER4 Write:
Freescale Semiconductor, Inc...
32
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$00A0 - $00C7
Address $00B9 $00BA $00BB $00BC $00BD $00BE Name PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved
V02.15
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 0 0 Bit 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 Bit 2 2 2 2 2 2 2 2 2 2 2 2 PWM7IN 0 0 0 Bit 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Freescale Semiconductor, Inc...
$00BF $00C0 $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7
PWMRS PWMLVL TRT 0 0 0 0 0 0
PWM7IN PWM7E L NA 0 0 0 0 0 0
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
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Freescale MC9S12DP256B Device User Guide -- V02.15
$00D0 - $00D7
Address $00D0 $00D1 $00D2 $00D3 $00D4 $00D5 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL
Semiconductor, Inc.
SCI1 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
Freescale Semiconductor, Inc...
$00D6 $00D7
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI0 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
$00E0 - $00E7
Address $00E0 $00E1 $00E2 $00E3 Name IBAD IBFD IBCR IBSR Read: Write: Read: Write: Read: Write: Read: Write:
IIC (Inter IC Bus)
Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 IBIF Bit 0 0 IBC0 IBSWAI RXAK
34 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$00E0 - $00E7
Address $00E4 $00E5 $00E6 $00E7 Name IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write:
V02.15
IIC (Inter IC Bus)
Bit 7 D7 0 0 0 Bit 6 D6 0 0 0 Bit 5 D5 0 0 0 Bit 4 D4 0 0 0 Bit 3 D3 0 0 0 Bit 2 D2 0 0 0 Bit 1 D1 0 0 0 Bit 0 D0 0 0 0
$00E8 - $00EF
Address Name DLCBCR1 DLCBSVR DLCBCR2 DLCBDR DLCBARD DLCBRSR DLCSCR DLCBSTAT
BDLC (Bytelevel Data Link Controller J1850)
Bit 7 Read: IMSG Write: Read: 0 Write: Read: SMRST Write: Read: D7 Write: Read: 0 Write: 0 Read: Write: 0 Read: Write: 0 Read: Write: Bit 6 CLKS 0 DLOOP D6 RXPOL 0 0 0 Bit 5 0 I3 RX4XE D5 0 R5 0 0 Bit 4 0 I2 NBFS D4 0 R4 BDLCE 0 Bit 3 0 I1 TEOD D3 BO3 R3 0 0 Bit 2 0 I0 TSIFR D2 BO2 R2 0 0 Bit 1 IE 0 TMIFR1 D1 BO1 R1 0 0 Bit 0 WCM 0 TMIFR0 D0 BO0 R0 0 IDLE
Freescale Semiconductor, Inc...
$00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF
$00F0 - $00F7
Address $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6 $00F7 Name SPI1CR1 SPI1CR2 SPI1BR SPI1SR Reserved SPI1DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI1 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
35 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12DP256B Device User Guide -- V02.15
$00F8 - $00FF
Address $00F8 $00F9 $00FA $00FB $00FC $00FD Name SPI2CR1 SPI2CR2 SPI2BR SPI2SR Reserved SPI2DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
SPI2 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
Freescale Semiconductor, Inc...
$00FE $00FF
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B $010C Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD Reserved for Factory Test FADDRHI FADDRLO FDATAHI FDATALO Reserved
Flash Control Register (fts512k4)
Bit 7 Bit 6 Read: FDIVLD PRDIV8 Write: Read: KEYEN NV6 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: FPOPEN NV6 Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 Bit 14 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Read: 0 0 Write: Bit 5 FDIV5 NV5 0 KEYACC FPHDIS PVIOL CMDB5 0 Bit 4 FDIV4 NV4 WRALL 0 FPHS1 ACCERR 0 0 Bit 3 FDIV3 NV3 0 0 FPHS0 0 0 0 Bit 2 FDIV2 NV2 0 0 FPLDIS BLANK CMDB2 0 Bit 1 FDIV1 SEC1 0 BKSEL1 FPLS1 0 0 0 Bit 0 FDIV0 SEC0 0 BKSEL0 FPLS0 0 CMDB0 0
13 5 13 5 0
12 4 12 4 0
11 3 11 3 0
10 2 10 2 0
9 1 9 1 0
Bit 8 Bit 0 Bit 8 Bit 0 0
36 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0100 - $010F
Address $010D $010E $010F Name Reserved Reserved Reserved Read: Write: Read: Write: Read: Write:
V02.15
Flash Control Register (fts512k4)
Bit 7 0 0 0 Bit 6 0 0 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0
$0110 - $011B
Address $0110 Name ECLKDIV Reserved Reserved for Factory Test ECNFG EPROT ESTAT ECMD Reserved for Factory Test EADDRHI EADDRLO EDATAHI EDATALO
EEPROM Control Register (eets4k)
Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: EPOPEN NV6 Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Bit 5 EDIV5 0 0 0 NV5 PVIOL CMDB5 0 0 5 13 5 Bit 4 EDIV4 0 0 0 NV4 ACCERR 0 0 0 4 12 4 Bit 3 EDIV3 0 0 0 EPDIS 0 0 0 0 3 11 3 Bit 2 EDIV2 0 0 0 EP2 BLANK CMDB2 0 Bit 1 EDIV1 0 0 0 EP1 0 0 0 Bit 0 EDIV0 0 0 0 EP0 0 CMDB0 0
Freescale Semiconductor, Inc...
$0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 $0119 $011A $011B
10 2 10 2
9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0
$011C - $011F
Address $011C $011D $011E $011F Name Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write:
Reserved for RAM Control Register
Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0
37 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12DP256B Device User Guide -- V02.15
$0120 - $013F
Address $0120 $0121 $0122 $0123 $0124 $0125 Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0 ATD1TEST1 Reserved ATD1STAT1 Reserved ATD1DIEN Reserved PORTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H
Semiconductor, Inc.
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 5 0 5 13 0 13 0 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 2 0 2 10 0 10 0 10 0 10 0 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 1 0 1 9 0 9 0 9 0 9 0 9 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 4 0 4 12 0 12 0 12 0 12 0 12 S1C PRS3 0 0 0 0 0 0 CCF3 0 3 0 3 11 0 11 0 11 0 11 0 11
Freescale Semiconductor, Inc...
$0126 $0127 $0128 $0129 $012A $012B $012C $012D $012E $012F $0130 $0131 $0132 $0133 $0134 $0135 $0136 $0137 $0138
38 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0120 - $013F
Address $0139 $013A $013B $013C $013D $013E Name ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
V02.15
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0
Freescale Semiconductor, Inc...
$013F
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D $014E $014F Name Read: CAN0CTL0 Write: Read: CAN0CTL1 Write: Read: CAN0BTR0 Write: Read: CAN0BTR1 Write: Read: CAN0RFLG Write: Read: CAN0RIER Write: Read: CAN0TFLG Write: Read: CAN0TIER Write: Read: CAN0TARQ Write: Read: CAN0TAAK Write: Read: CAN0TBSEL Write: Read: CAN0IDAC Write: Read: Reserved Write: Read: Reserved Write: Read: CAN0RXERR Write: Read: CAN0TXERR Write:
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME 0 BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
39 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12DP256B Device User Guide -- V02.15
$0140 - $017F
Address Name CAN0IDAR0 $0150 $0153 CAN0IDAR3 $0154 - CAN0IDMR0 $0157 CAN0IDMR3 CAN0IDAR4 $0158 $015B CAN0IDAR7 $015C - CAN0IDMR4 $015F CAN0IDMR7 $0160 CAN0RXFG $016F $0170 CAN0TXFG $017F Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 AC7 AM7 AC7 AM7 Bit 6 AC6 AM6 AC6 AM6 Bit 5 AC5 AM5 AC5 AM5 Bit 4 AC4 AM4 AC4 AM4 Bit 3 AC3 AM3 AC3 AM3 Bit 2 AC2 AM2 AC2 AM2 Bit 1 AC1 AM1 AC1 AM1 Bit 0 AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2
Freescale Semiconductor, Inc...
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xxx0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Extended ID Read: CANxTIDR1 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$xxx1
ID9
ID8
ID7
$xxx2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xxx3 $xxx4$xxxB $xxxC $xxxD $xxxE $xxxF
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10 ID20 ID2
TSR14 TSR6 ID27 ID9 ID19 ID1
TSR13 TSR5 ID26 ID8 ID18 ID0
TSR12 TSR4 ID25 ID7 SRR=1 RTR
TSR11 TSR3 ID24 ID6 IDE=1 IDE=0
TSR10 TSR2 ID23 ID5 ID17
TSR9 TSR1 ID22 ID4 ID16
TSR8 TSR0 ID21 ID3 ID15
$xx10
$xx10
40 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
V02.15
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xx12 Name Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID CANxTDSR0 CANxTDSR7 CANxTDLR CONxTTBPR CANxTTSRH CANxTTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID14 Bit 6 ID13 Bit 5 ID12 Bit 4 ID11 Bit 3 ID10 Bit 2 ID9 Bit 1 ID8 Bit 0 ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xx13 $xx14$xx1B $xx1C
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
Freescale Semiconductor, Inc...
$xx1D $xx1E $xx1F
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $01BF
Address $0180 $0181 $0182 $0183 $0184 $0185 $0186 $0187 $0188 $0189 $018A $018B $018C Name
CAN1 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CAN1CTL0 Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM CAN1CTL1 Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN1BTR0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CAN1BTR1 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF CAN1RFLG Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE CAN1RIER Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 CAN1TFLG Write: Read: 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 CAN1TIER Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 CAN1TARQ Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 CAN1TAAK Write: Read: 0 0 0 0 0 TX2 TX1 TX0 CAN1TBSEL Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CAN1IDAC Write: Read: 0 0 0 0 0 0 0 0 Reserved Write:
41 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12DP256B Device User Guide -- V02.15
$0180 - $01BF
Address $018D $018E $018F $0190 $0191 $0192 Name
Semiconductor, Inc.
CAN1 (Motorola Scalable CAN - MSCAN)
Freescale Semiconductor, Inc...
$0193 $0194 $0195 $0196 $0197 $0198 $0199 $019A $019B $019C $019D $019E $019F $01A0 $01AF $01B0 $01BF
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CAN1RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CAN1TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR7 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR4 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR5 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR6 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR7 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-2 CAN1RXFG Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-2 CAN1TXFG Write:
42 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$01C0 - $01FF
Address $01C0 $01C1 $01C2 $01C3 $01C4 $01C5 Name Read: CAN2CTL0 Write: Read: CAN2CTL1 Write: Read: CAN2BTR0 Write: Read: CAN2BTR1 Write: Read: CAN2RFLG Write: Read: CAN2RIER Write: Read: CAN2TFLG Write: Read: CAN2TIER Write: Read: CAN2TARQ Write: Read: CAN2TAAK Write: Read: CAN2TBSEL Write: Read: CAN2IDAC Write: Read: Reserved Write: Read: Reserved Write: Read: CAN2RXERR Write: Read: CAN2TXERR Write: Read: CAN2IDAR0 Write: Read: CAN2IDAR1 Write: Read: CAN2IDAR2 Write: Read: CAN2IDAR3 Write: Read: CAN2IDMR0 Write: Read: CAN2IDMR1 Write: Read: CAN2IDMR2 Write: Read: CAN2IDMR3 Write: Read: CAN2IDAR4 Write:
V02.15
CAN2 (Motorola Scalable CAN - MSCAN)
Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME 0 BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
Freescale Semiconductor, Inc...
$01C6 $01C7 $01C8 $01C9 $01CA $01CB $01CC $01CD $01CE $01CF $01D0 $01D1 $01D2 $01D3 $01D4 $01D5 $01D6 $01D7 $01D8
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0
43 For More Information On This Product, Go to: www.freescale.com
Freescale MC9S12DP256B Device User Guide -- V02.15
$01C0 - $01FF
Address $01D9 $01DA $01DB $01DC $01DD $01DE Name CAN2IDAR5 CAN2IDAR6 CAN2IDAR7 CAN2IDMR4 CAN2IDMR5 CAN2IDMR6 CAN2IDMR7 CAN2RXFG CAN2TXFG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
CAN2 (Motorola Scalable CAN - MSCAN)
Bit 7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AC0 AC0 AC0 AM0 AM0 AM0 AM0
Freescale Semiconductor, Inc...
$01DF $01E0 $01EF $01F0 $01FF
FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2
$0200 - $023F
Address $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C Name
CAN3 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CAN3CTL0 Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM CAN3CTL1 Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN3BTR0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CAN3BTR1 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF CAN3RFLG Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE CAN3RIER Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 CAN3TFLG Write: Read: 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 CAN3TIER Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 CAN3TARQ Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 CAN3TAAK Write: Read: 0 0 0 0 0 TX2 TX1 TX0 CAN3TBSEL Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CAN3IDAC Write: Read: 0 0 0 0 0 0 0 0 Reserved Write:
44 For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0200 - $023F
Address $020D $020E $020F $0210 $0211 $0212 Name
V02.15
CAN3 (Motorola Scalable CAN - MSCAN)
Freescale Semiconductor, Inc...
$0213 $0214 $0215 $0216 $0217 $0218 $0219 $021A $021B $021C $021D $021E $021F $0220 $022F $0230 $023F
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CAN3RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CAN3TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN3IDAR7 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR4 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR5 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR6 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN3IDMR7 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-2 CAN3RXFG Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-2 CAN3TXFG Write:
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Freescale MC9S12DP256B Device User Guide -- V02.15
$0240 - $027F
Address $0240 $0241 $0242 $0243 $0244 $0245 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Semiconductor, Inc.
PIM (Port Integration Module PIM_9DP256)
Bit 7 PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 PTM7 PTIM7 DDRM7 RDRM7 PERM7 PPSM7 Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 PTM6 PTIM6 DDRM7 RDRM6 PERM6 PPSM6 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0
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$0246 $0247 $0248 $0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP7 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0240 - $027F
Address $0259 $025A $025B $025C $025D $025E Name PTIP DDRP RDRP PERP PPSP PIEP PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read:
V02.15
PIM (Port Integration Module PIM_9DP256)
Bit 7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 PTH7 PTIH7 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 Bit 6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 PTH6 PTIH6 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 Bit 5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 PTH5 PTIH5 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 0 0 0 Bit 4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 PTH4 PTIH4 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 0 0 0 Bit 3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 PTH3 PTIH3 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0 Bit 2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 PTH2 PTIH2 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 0 0 0 0 0 0 0 0 Bit 1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 PTH1 PTIH1 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 Bit 0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0
Freescale Semiconductor, Inc...
$025F $0260 $0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D $026E $026F $0270 $027F
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Freescale MC9S12DP256B Device User Guide -- V02.15
$0280 - $02BF
Address $0280 $0281 $0282 $0283 $0284 $0285 Name Read: CAN4CTL0 Write: Read: CAN4CTL1 Write: Read: CAN4BTR0 Write: Read: CAN4BTR1 Write: Read: CAN4RFLG Write: Read: CAN4RIER Write: Read: CAN4TFLG Write: Read: CAN4TIER Write: Read: CAN4TARQ Write: Read: CAN4TAAK Write: Read: CAN4TBSEL Write: Read: CAN4IDAC Write: Read: Reserved Write: Read: Reserved Write: Read: CAN4RXERR Write: Read: CAN4TXERR Write: Read: CAN4IDAR0 Write: Read: CAN4IDAR1 Write: Read: CAN4IDAR2 Write: Read: CAN4IDAR3 Write: Read: CAN4IDMR0 Write: Read: CAN4IDMR1 Write: Read: CAN4IDMR2 Write: Read: CAN4IDMR3 Write: Read: CAN4IDAR4 Write:
Semiconductor, Inc.
CAN4 (Motorola Scalable CAN - MSCAN)
Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME 0 BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
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$0286 $0287 $0288 $0289 $028A $028B $028C $028D $028E $028F $0290 $0291 $0292 $0293 $0294 $0295 $0296 $0297 $0298
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
$0280 - $02BF
Address $0299 $029A $029B $029C $029D $029E Name CAN4IDAR5 CAN4IDAR6 CAN4IDAR7 CAN4IDMR4 CAN4IDMR5 CAN4IDMR6 CAN4IDMR7 CAN4RXFG CAN4TXFG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
V02.15
CAN4 (Motorola Scalable CAN - MSCAN)
Bit 7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AC0 AC0 AC0 AM0 AM0 AM0 AM0
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$029F $02A0 $02AF $02B0 $02BF
FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2
$02C0 - $03FF
Address $02C0 - $03FF Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID number. Table 1-3 Assigned Part ID Numbers
Device MC9S12DP256 MC9S12DP256 MC9S12DP256 Mask Set Number 0K79X 1K79X 2K79X Part ID1 $0010 $0011 $0012
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
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Freescale MC9S12DP256B Device User Guide -- V02.15
Semiconductor, Inc.
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to section Module Mapping and Control (MMC) of HCS12 Core User Guide for further details.
Table 1-4 Memory size registers
Register name MEMSIZ0 MEMSIZ1 Value $25 $81
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
V02.15
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12DP256B/MC9S12DT256/MC9S12DJ256 and MC9S12DG256 is available in a 112-pin low profile quad flat pack (LQFP) and MC9S12DJ256 is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-3 show the pin assignments.
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Freescale MC9S12DP256B Device User Guide -- V02.15
Semiconductor, Inc.
Freescale Semiconductor, Inc...
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 MOSI2/KWH5/PH5 MISO2/KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ECS VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4 PM7/TXCAN3/TXCAN4 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12DP256B/MC9S12DT256 /MC9S12DJ256/MC9S12DG256
VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 80 Pin Package
Figure 2-1 Pin Assignments in 112-pin LQFP
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
V02.15
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Freescale Semiconductor, Inc...
MC9S12DG256
80 QFP
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DG256
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Freescale MC9S12DP256B Device User Guide -- V02.15
Semiconductor, Inc.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Freescale Semiconductor, Inc...
MC9S12DJ256
80 QFP
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 2-3 Pin Assignments in 80-pin QFP for MC9S12DJ256
2.2 Signal Properties Summary
Table 2-1summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package.
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Table 2-1 Signal Properties
Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
V02.15
Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply
EXTAL XTAL RESET TEST VREGEN XFC BKGD -- -- -- -- -- -- TAGHI -- -- -- -- -- -- MODC -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDPLL VDDPLL VDDR N.A. VDDX VDDPLL VDDR
Internal Pull Resistor
CTRL NA NA None NA NA NA Always Up Reset State NA NA None NA NA NA Up
Description
Oscillator Pins External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug, Tag High, Mode Input Port AD Input, Analog Input AN7
Freescale Semiconductor, Inc...
PAD[15]
AN1[7]
ETRIG1
--
--
VDDA
None
None
of ATD1, External Trigger Input of ATD1
PAD[14:8]
AN1[6:0]
--
--
--
VDDA
None
None
Port AD Inputs, Analog Inputs AN[6:0] of ATD1 Port AD Input, Analog Input AN7 of ATD0, External Trigger Input of ATD0 Port AD Inputs, Analog Inputs AN[6:0] of ATD0 Port A I/O, Multiplexed Address/Data Port B I/O, Multiplexed Address/Data Port E I/O, Access, Clock Select Port E I/O, Pipe Status, Mode Input
PAD[7]
AN0[7]
ETRIG0
--
--
VDDA
None
None
PAD[6:0] PA[7:0] PB[7:0] PE7 PE6
AN0[6:0] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1
-- -- -- XCLKS MODB
-- -- -- -- --
-- -- -- -- --
VDDA VDDR VDDR VDDR VDDR
None PUCR PUCR PUCR
None Disabled Disabled Up
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR Up Up Up
PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6
IPIPE0 ECLK LSTRB R/W IRQ XIRQ KWH7 KWH6
MODA -- TAGLO -- -- -- SS2 SCK2
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR
Port E I/O, Pipe Status, Mode Input Port E I/O, Bus Clock Output Port E I/O, Byte Strobe, Tag Low Port E I/O, R/W in expanded modes Port E Input, Maskable Interrupt
Always up Port E Input, Non Maskable Interrupt PERH/ PPSH PERH/ PPSH Disabled Disabled Port H I/O, Interrupt, SS of SPI2 Port H I/O, Interrupt, SCK of SPI2
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Freescale MC9S12DP256B Device User Guide -- V02.15
Semiconductor, Inc.
Internal Pull Resistor
CTRL PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERJ/ PPSJ PERJ/ PPSJ PERJ/ PSJ PUCR PUCR PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERP/ PPSP Reset State Disabled Disabled Disabled Disabled Disabled Disabled Up
Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply
Description
PH5 PH4 PH3 PH2 PH1
KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 KWJ7
MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 TXCAN4
-- -- -- -- -- -- SCL
-- -- -- -- -- -- TXCAN0
VDDR VDDR VDDR VDDR VDDR VDDR VDDX
Port H I/O, Interrupt, MOSI of SPI2 Port H I/O, Interrupt, MISO of SPI2 Port H I/O, Interrupt, SS of SPI1 Port H I/O, Interrupt, SCK of SPI1 Port H I/O, Interrupt, MOSI of SPI1 Port H I/O, Interrupt, MISO of SPI1 Port J I/O, Interrupt, TX of CAN4, SCL of IIC, TX of CAN0 Port J I/O, Interrupt, RX of CAN4, SDA of IIC, RX of CAN0 Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses Port M I/O, TX of CAN3, TX of CAN4 Port M I/O, RX of CAN3, RX of CAN4 Port M I/O, TX of CAN2, CAN0, CAN4, SCK of SPI0 Port M I/O, RX of CAN2, CAN0, CAN4, MOSI of SPI0 Port M I/O, TX of CAN1, CAN0, SS of SPI0 Port M I/O, RX of CAN1, CAN0, MISO of SPI0 Port M I/O, TX of CAN0, TX of BDLC Port M I/O, RX of CAN0, RX of BDLC Port P I/O, Interrupt, Channel 7 of PWM, SCK of SPI2
Freescale Semiconductor, Inc...
PH0 PJ7
PJ6 PJ[1:0] PK7 PK[5:0] PM7
KWJ6 KWJ[1:0] ECS XADDR [19:14] TXCAN3
RXCAN4 -- ROMONE -- TXCAN4
SDA -- -- -- --
RXCAN0 -- -- -- --
VDDX VDDX VDDX VDDX VDDX
Up Up Up Up Disabled
PM6
RXCAN3
RXCAN4
--
--
VDDX
Disabled
PM5
TXCAN2
TXCAN0
TXCAN4
SCK0
VDDX
Disabled
PM4
RXCAN2
RXCAN0
RXCAN4
MOSI0
VDDX
Disabled
PM3
TXCAN1
TXCAN0
--
SS0
VDDX
Disabled
PM2 PM1 PM0 PP7
RXCAN1 TXCAN0 RXCAN0 KWP7
RXCAN0 TXB RXB PWM7
-- -- -- SCK2
MISO0 -- -- --
VDDX VDDX VDDX VDDX
Disabled Disabled Disabled Disabled
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Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Internal Pull Resistor
CTRL PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST Reset State Disabled
V02.15
Description
PP6
KWP6
PWM6
SS2
--
VDDX
Port P I/O, Interrupt, Channel 6 of PWM, SS of SPI2 Port P I/O, Interrupt, Channel 5 of PWM, MOSI of SPI2 Port P I/O, Interrupt, Channel 4 of PWM, MISO2 of SPI2 Port P I/O, Interrupt, Channel 3 of PWM, SS of SPI1 Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1 Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1 Port P I/O, Interrupt, Channel 0 of PWM, MISO2 of SPI1 Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 Port S I/O, MOSI of SPI0 Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0 Port T I/O, Timer channels
PP5
KWP5
PWM5
MOSI2
--
VDDX
Disabled
PP4
KWP4
PWM4
MISO2
--
VDDX
Disabled
PP3
KWP3
PWM3
SS1
--
VDDX
Disabled
Freescale Semiconductor, Inc...
PP2
KWP2
PWM2
SCK1
--
VDDX
Disabled
PP1
KWP1
PWM1
MOSI1
--
VDDX
Disabled
PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0]
KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
PWM0 -- -- -- -- -- -- -- -- --
MISO1 -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Disabled Up Up Up Up Up Up Up Up Disabled
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
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2.3.2 RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
2.3.3 TEST -- Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN -- Voltage Regulator Enable Pin
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This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC -- PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R0 MCU CS VDDPLL VDDPLL
CP
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1.
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide -- 2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1
V02.15
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD1.
2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0
PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0
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PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL.
2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
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2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
2.3.16 PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3
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PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.18 PE2 / R/W -- Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ -- Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.21 PH7 / KWH7 / SS2 -- Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.22 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide -- 2.3.23 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5
V02.15
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.24 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.25 PH3 / KWH3 / SS1 -- Port H I/O Pin 3
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PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.28 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
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2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode .
2.3.32 PK7 / ECS / ROMONE -- Port K I/O Pin 7
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PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU normal expanded wide and narrow modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the state of this pin is latched to the ROMON bit.
2.3.33 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 / TXCAN3 / TXCAN4 -- Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4).
2.3.35 PM6 / RXCAN3 / RXCAN4 -- Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4).
2.3.36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide -- 2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3
V02.15
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
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2.3.40 PM1 / TXCAN0 / TXB -- Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin TXB of the BDLC.
2.3.41 PM0 / RXCAN0 / RXB -- Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin RXB of the BDLC.
2.3.42 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.43 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
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2.3.45 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.46 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
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2.3.47 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.50 PS7 / SS0 -- Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
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V02.15
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.54 PS3 / TXD1 -- Port S I/O Pin 3
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PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
2.3.55 PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12DP256B power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application.
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2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
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2.4.3 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator.
NOTE:
No load allowed except for bypass capacitors.
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Freescale Semiconductor, Inc. MC9S12DP256B Device User Guide --
Table 2-2 MC9S12DP256 Power and Ground Connection Summary
Mnemonic VDD1, 2 VSS1, 2 VDDR VSSR VDDX VSSX VDDA VSSA Pin Number 112-pin QFP 13, 65 14, 66 41 40 107 106 83 86 85 84 43 45 97 Nominal Voltage 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 0V 5.0 V 2.5 V 0V 5V Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers.
V02.15
Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable
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VRL VRH VDDPLL VSSPLL VREGEN
2.4.7 VREGEN -- On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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V02.15
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.
1/2
BDM
S12_CORE
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core clock
Flash RAM EEPROM EXTAL ECT ATD0, 1 CRG bus clock oscillator clock XTAL PWM SCI0, SCI1 SPI0, 1, 2 CAN0, 1, 2, 3, 4 IIC BDLC PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DP256B. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device.
4.2 Chip Configuration Summary
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The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0 0 0 0 1 1 1 1
PE6 = MODB
0 0 1 1 0 0 1 1
PE5 = MODA
0 1 0 1 0 1 0 1
PK7 = ROMCTL
X X X X X 0 1 X 0 1
ROMON Bit
1 0 0 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the Core User Guide.
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1 0
Description
Colpitts Oscillator selected External clock selected
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Table 4-3 Voltage Regulator VREGEN
VREGEN
1 0
Description
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows:
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* * * *
Protection of the contents of FLASH, Protection of the contents of EEPROM, Operation in single-chip mode, Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
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In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
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4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
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Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB
Interrupt Source
Reset Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 Enhanced Capture Timer channel 3 Enhanced Capture Timer channel 4 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 ATD1 Port J Port H Modulus Down Counter underflow
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SP0CR1 (SPIE, SPTIE) SC0CR2 (TIE, TCIE, RIE, ILIE) SC1CR2 (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) ATD1CTL2 (ASCIE) PTJIF (PTJIE) PTHIF(PTHIE) MCCTL(MCZI)
HPRIO Value to Elevate
- - - - - - $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $CE $CC $CA
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$FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9 $FFA6, $FFA7 $FFA4, $FFA5 $FFA2, $FFA3 $FFA0, $FFA1 $FF9E, $FF9F $FF9C, $FF9D $FF9A, $FF9B $FF98, $FF99 $FF96, $FF97 $FF94, $FF95 $FF92, $FF93 $FF90, $FF91 $FF8E, $FF8F $FF8C, $FF8D $FF80 to $FF8B CRG PLL lock CRG Self Clock Mode BDLC IIC Bus SPI1 SPI2 EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit CAN2 wake-up CAN2 errors CAN2 receive CAN2 transmit CAN3 wake-up CAN3 errors CAN3 receive CAN3 transmit CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit Port P Interrupt
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I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE) DLCBCR1(IE) IBCR (IBIE) SP1CR1 (SPIE, SPTIE) SP2CR1 (SPIE, SPTIE) EECTL(CCIE, CBEIE) FCTL(CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE2-TXEIE0) CAN1RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) CAN1TIER (TXEIE2-TXEIE0) CAN2RIER (WUPIE) CAN2RIER (CSCIE, OVRIE) CAN2RIER (RXFIE) CAN2TIER (TXEIE2-TXEIE0) CAN3RIER (WUPIE) CAN3RIER (TXEIE2-TXEIE0) CAN3RIER (RXFIE) CAN3TIER (TXEIE2-TXEIE0) CAN4RIER (WUPIE) CAN4RIER (CSCIE, OVRIE) CAN4RIER (RXFIE) CAN4TIER (TXEIE2-TXEIE0) PTPIF (PTPIE) PWMSDN (PWMIE) $C8 $C6 $C4 $C2 $C0 $BE $BC $BA $B8 $B6 $B4 $B2 $B0 $AE $AC $AA $A8 $A6 $A4 $A2 $A0 $9E $9C $9A $98 $96 $94 $92 $90 $8E $8C
Pulse Accumulator B Overflow
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PWM Emergency Shutdown
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
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NOTE:
For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
V02.15
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
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Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM). Table 6-1 Configuration of HCS12 Core
Name PUCR_RESET NUM_INT INITEE_RST INITEE_WOK Description PUCR reset state Interrupt Request Bus Width INITEE reset state INITEE Write anytime in normal mode PPAGE Write only in special mode MC9S12DP256B Configuration $90 56 $01 INITEE register is writeable once in normal modes PPAGE register is writable in all modes,reset state of the PPAGE register is $00
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PPAGE_SMOD_ONLY
Section 7 Clock and Reset Generator (CRG) Block Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7).
Section 8 Enhanced Capture Timer (ECT) Block Description
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP256B. Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module.
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Section 10 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 11 Serial Communications Interface (SCI) Block Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DP256B device. Consult the SCI Block User Guide for information about each Serial Communications Interface module.
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Section 12 Serial Peripheral Interface (SPI) Block Description
There are three Serial Peripheral Interfaces(SPI2, SPI1 and SPI0) implemented on MC9S12DP256B. Consult the SPI Block User Guide for information about each Serial Peripheral Interface module.
Section 13 J1850 (BDLC) Block Description
Consult the BDLC Block User Guide for information about the J1850 module.
Section 14 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module.
Section 15 Flash EEPROM 256K Block Description
Consult the FTS256K Block User Guide for information about the flash module.
Section 16 EEPROM 4K Block Description
Consult the EETS4K Block User Guide for information about the EEPROM module.
Section 17 RAM Block Description
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This module supports single-cycle misaligned word accesses.
V02.15
Section 18 MSCAN Block Description
There are five MSCAN modules (CAN4, CAN3, CAN2, CAN1 and CAN0) implemented on the MC9S12DP256B. Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module.
Section 19 Port Integration Module (PIM) Block Description
Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module.
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Section 20 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 Q1
Purpose VDD1 filter cap VDD2 filter cap VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap
Type ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value 100 .. 220nF 100 .. 220nF 100nF >=100nF 100nF >=100nF
See PLL specification chapter DC cutoff cap PLL loop filter res Quartz
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed:
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* * * * * * *
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Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins(C1 - C6). Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
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Figure 20-1 Recommended PCB Layout 112 LQFP
VREGEN
VDDX
C6 VSSX
VSSA
C3
VDDA
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VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR C4 VDDR C5 C9 R1 C10 C8 Q1 VSSPLL VDDPLL C7
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C11
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Figure 20-2 Recommended PCB Layout for 80QFP
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1
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VSS2
C1 C2
VSS1 VDD2
VSSR C4 C5 VDDR C11
C8
C7 Q1
C10
R1
C9
VSSPLL VDDPLL
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Appendix A Electrical Characteristics
A.1 General
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.
This supplement contains the most accurate electrical information for the MC9S12DP256B microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change.
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This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE:
P:
This classification is shown in the column labeled "C" in the parameter tables where appropriate.
Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12DP256B utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
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The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.
NOTE:
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In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator.
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Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1
Num
1 2 3 4 5 6 7 8 9 10 11 12 13
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Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous Maximum Current Single pin limit for TEST 5 Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST ID IDL IDT T
stg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 - 65
Max
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155
Unit
V V V V V V V V V mA mA mA C
NOTES: 1. Beyond absolute maximum ratings device might be damaged.
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2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V
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Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5
Unit
Ohm pF
Ohm pF
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
1 2 3 4
Rating
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
C Human Body Model (HBM) C Machine Model (MM) C Charge Device Model (CDM) Latch-up Current at TA = 125C C positive negative Latch-up Current at TA = 27C C positive negative
5
ILAT
-
mA
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This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus
Min
4.5 2.35 2.35 -0.1 -0.1 0.5 0.5
Typ
5 2.5 2.5 0 0 -
Max
5.25 2.75 2.75 0.1 0.1 16 25
Unit
V V V V V MHz MHz
I/O, Regulator and Analog Supply Voltage
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Digital Logic Supply Voltage 1 PLL Supply Voltage 2 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12DP256BC Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12DP256BV Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12DP256BM Operating Junction Temperature Range Operating Ambient Temperature Range 2
TJ T
A
-40 -40
27
100 85
C C
TJ TA
-40 -40
27
120 105
C C
TJ TA
-40 -40
27
140 125
C C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
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T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO
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P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 - V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Table A-5 Thermal Package Characteristics1
Num C
1 2 3 4
Rating
Symbol
JA JA JA JA
Min
-
Typ
-
Max
54 41 51 41
Unit
oC/W o
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3
C/W
T Thermal Resistance LQFP 80, single sided PCB T Thermal Resistance LQFP 80, double sided PCB with 2 internal planes
oC/W oC/W
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NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5 -
Unit
V V V V mV A
VIH V
IL
VIL V
HYS
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4
Input Leakage Current (pins in high impedance input P mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) P Partial Drive IOH = -2mA Full Drive IOH = -10mA Output Low Voltage (pins in output mode) P Partial Drive IOL = +2mA Full Drive IOL = +10mA Internal Pull Up Device Current, P tested at V Max.
IL
I
in
-2.5
-
2.5
5
V
OH
VDD5 - 0.8
-
-
V
6
V
OL
-
-
0.8
V
7
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
-
-
-130
A A A A pF mA s s
8
Internal Pull Up Device Current, P tested at V Min.
IH
-10
-
-
9
Internal Pull Down Device Current, P tested at V Min.
IH
-
-
130
10 11 12
Internal Pull Down Device Current, P tested at V Max.
IL
10
6
2.5 25 3
D Input Capacitance Injection current2 T Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse filtered3 P Port H, J, P Interrupt Input Pulse passed3
-2.5 -25
-
13 14
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
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given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on only RTI enabled 1 Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Stop Current 2 -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
Symbol
IDD5 IDDW
Min
Typ
Max
65 40 5
Unit
mA
2
P P C P C C P C P C P C C C C C C C C P C C P C P C P
mA
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3
IDDPS
370 400 450 550 600 650 800 850 1200 570 600 650 750 850 1200 1500 12 25 100 130 160 200 350 400 600
500 A
1600 2100 5000
4
IDDPS
A
100 A
5
IDDS
1200 1700 5000
NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed
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A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics
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Conditions are shown in Table A-4 unless otherwise noted
Num C
Reference Potential 1 2 3 4 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 4.50 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period D
5.00
5.25 2.0 28 14 26 13 20 0.750 0.375
Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK
5
D
NCONV8 TCONV8 tREC IREF IREF
6 7 8
D Recovery Time (VDDA=5.0 Volts) P P Reference Supply current 2 ATD blocks on Reference Supply current 1 ATD block on
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
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specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider.
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1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5
Rating
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 22
Unit
K pF mA A/A A/A
C Max input Source Resistance Total Input Capacitance T Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection
-2.5
2.5 10-4 10-2
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Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num C
1 2 3 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error1
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
5
Max
Unit
mV
-1 -2.5 -3 1.5 2.0 20 -0.5 -1.0 -1.5 0.5 1.0
1 2.5 3
Counts Counts Counts mV
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4 5 6 7 8
0.5 1.0 1.5
Counts Counts Counts
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ----------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn - V0 DNL ( i ) = ------------------- - n 1LSB
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DNL
LSB Vi-1
$3FF $3FE $3FD $3FC
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
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$3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1 ATD Accuracy Definitions
NOTE:
Figure A-1 shows only definitions, for specification values refer to Table A-10.
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8-Bit Resolution
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A.3 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured.
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The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus
A.3.1.2 Burst Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Burst programming is more than 2 times faster than single word programming.
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A.3.1.3 Sector Erase
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Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1 t era 4000 --------------------f NVMOP
The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes:
1 t mass 20000 --------------------f NVMOP
The setup time can be ignored for this operation.
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A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check location t cyc + 10 t cyc
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
Min
0.5 1 150 46 2 20.4 2 678.4 2 20 5 100 5 11 6 11 6
Typ
Max
50 1
Unit
MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 32 Words 4 P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block
200 74.5 3 31 3 1035.5 3 26.7 3 133 3 32778 7 20587
kHz s s s ms ms tcyc tcyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus.
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3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. urst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted.
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The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.
NOTE:
All values shown in Table A-12 are target values and subject to further extensive characterization.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Cycles
10 10,000
Data Retention Lifetime
15 5
Unit
Years Years
C Flash/EEPROM (-40C to + 125C) C EEPROM (-40C to + 125C)
NOTE: NOTE:
Flash cycling performance is 10 cycles at -40C to + 125C. Data retention is specified for 15 years. EEPROM cycling performance is 10K cycles at -40C to +125C. Data retention is specified for 5 years on words after cycling 10K times. However if only 10 cycles are executed on a word the data retention is specified for 15 years.
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A.4 Voltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL
Symbol
CLVDD CLVDDfcPLL
Min
Typ
220 220
Max
Unit
nF nF
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A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-14 Startup Characteristics
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Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 T POR release level T POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 196
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time
nosc ns tcyc
A.5.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
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A.5.1.4 Stop Recovery
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Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.5.2 Oscillator
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The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-15 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12
Rating
Symbol
fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS
Min
0.5 100
Typ
Max
16
Unit
MHz A
C Crystal oscillator range P Startup Current C Oscillator start-up time D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency3 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin
81 0.45 50 0.5 9.5 9.5 100
1002 2.5 200 50
ms s KHz MHz ns ns
1 1 9 1.1
ns ns pF V
NOTES: 1. fosc = 4MHz, C = 22pF. 2. Maximum value is for extreme cases using high Q, low frequency crystals 3. XCLKS =0 during reset
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The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
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Cs R Phase fosc fref 1 refdv+1 fcmp K Detector Loop Divider 1 synr+1
Cp
VCO KV fvco
1 2
Figure A-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-16. The VCO Gain at the desired VCO output frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V
KV = K1 e
The phase detector relationship is given by:
K = - i ch K V
ich is the current in tracking mode.
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The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------- ;( = 0.9 ) 4 50 50 2 + 1 +
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
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With the above inputs the resistance can be calculated as:
2 n fC R = ---------------------------K
The capacitance Cs can now be calculated as:
0.516 2 C s = --------------------- -------------- ;( = 0.9 ) fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external component selection (e.g. crystal, XFC filter). A.5.3.2 Jitter Information The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
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Figure A-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t max ( N ) t min ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
Figure A-4 Maximum bus clock jitter approximation
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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
Table A-16 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 50 4 1.5 2.5 8
Unit
MHz MHz %1 %1 %1 %1 ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
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D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay 2 D PLLON Tracking mode stabilization delay 2 D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 12 C Jitter fit parameter 22
0.5 0.3 0.2 -120 75 38.5 3.5 1.1 0.13
% %
NOTES: 1. % deviation from target frequency 2. fREF = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
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A.6 MSCAN
Table A-17 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
Unit
s s
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
5
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A.7 SPI
A.7.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-18.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)
1. If configured as output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
11
3
12
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6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 10
Figure A-5 SPI Master Timing (CPHA = 0)
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SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1. If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
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12
11
3
4
11
12
6 MSB IN2 BIT 6 . . . 1 10 LSB IN
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MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-6 SPI Master Timing (CPHA =1) Table A-18 SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 6 9 10 11 12 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi tv tho tr tf
Min
DC 4 1/2 1/2 tbus - 30 25 0
Typ
Max
1/4 2048 --
Unit
fbus tbus tsck tsck
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Data Valid (after Enable Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
1024 tbus
ns ns ns
25 0 25 25
ns ns ns ns
NOTES: 1. The numbers 7, 8 in the column labeled "Num" are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A-19.
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Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-19.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 9 MSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 4 4 11 12 8 10 10 12 11 3
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MISO (OUTPUT)
SLAVE 5
SLAVE LSB OUT
MOSI (INPUT)
Figure A-7 SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3
10 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure A-8 SPI Slave Timing (CPHA =1)
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Table A-19 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
1 1 2 3 4 5 P Operating Frequency
Rating
Symbol
fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf
Min
DC 4 1 1 tcyc - 30 25 25
Typ
Max
1/4 2048
Unit
fbus tbus tcyc tcyc ns ns ns
P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
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6 7 8 9 10 11 12
1 1 25 0 25 25
tcyc tcyc ns ns ns ns
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A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
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1, 2
3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 16
4
10 data
11
14 data
13
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17 Non-Multiplexed Addresses PK5:0 20 ECS PK7
18
19
21
22
23
24 R/W PE2
25
26
27 LSTRB PE3
28
29
30 NOACC PE7
31
32
33 IPIPO0 IPIPO1, PE6,5
34
35
36
Figure A-9 General External Bus Timing
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Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
V02.15
Num C
1 2 3 4 5 6 7
Rating
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 40 19 19
Typ
Max
25.0
Unit
MHz ns ns ns
P Frequency of operation (E-clock) P Cycle time D Pulse width, E low D Pulse width, E high1 D Address delay time D Address valid time to E rise (PWEL-tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time1 (PWEH-tDDW) D Address access time1 (tcyc-tAD-tDSR) D E high access time1 (PWEH-tDSR) D Non-multiplexed address delay time D Non-muxed address valid to E rise (PWEL-tNAD) D Non-multiplexed address hold time D Chip select delay time D Chip select access time1 (tcyc-tCSD-tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL-tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL-tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL-tNOD)
8 11 2 7 2 13 0 7 2 12 19 6 6 15 2 16 11 2 8 7 14 2 7 14 2 7 14
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
32 33 34 35 36 D NOACC hold time D IPIPO[1:0] delay time
Rating
Symbol
tNOH tP0D tP0V tP1D tP1V
Min
2 2 11 2 11
Typ
Max
Unit
ns
7
ns ns
D IPIPO[1:0] valid time to E rise (PWEL-tP0D) D IPIPO[1:0] delay time1 (PWEH-tP1V) D IPIPO[1:0] valid time to E fall
25
ns ns
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12DP256B packages.
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B.2 112-pin LQFP package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
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28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MAX MIN 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
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B.3 80-pin QFP package
L
60 61 41 40
S
S
B B P
D
L
H A-B
B
V 0.05 D
M
M
C A-B
-A-
-B-
S
S
D
0.20
0.20
-A-,-B-,-DDETAIL A
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DETAIL A
80 1 20
21
-D0.20
M
F
A H A-B S
S
D
S
0.05 A-B J
S
N
0.20 E C -CSEATING PLANE
M
C A-B
D
S
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B)
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User Guide End Sheet
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